1. Field of the Invention
The present invention relates to a transistor in a semiconductor device and method of fabricating the same, and more particularly, to a transistor in a semiconductor device and method of fabricating the same, in which gate oxide films of different thickness are formed in a high voltage device region and a low voltage device region.
2. Background of the Related Art
In general, the semiconductor device such as the transistor can be classified into a device driven by a high voltage and a device driven by a low voltage. For this reason, in a high voltage operating transistor and a low voltage operating transistor have, the thickness of the gate oxide film is different. A method of forming the gate oxide films having different thickness in the high voltage device region and the low voltage device region, respectively, will be described in short.
A first gate oxide film is first formed in a first thickness on the entire structure of the semiconductor substrate. After forming a photoresist pattern through which only the low voltage device region is opened, the first gate oxide film formed in the low voltage device region is removed. Next, the photoresist pattern is removed. A second gate oxide film is then formed in a second thickness on the entire structure. Thereby, a thick gate oxide film on which the first and second gate oxide films are stacked is formed in the high voltage device region and only the second gate oxide film is formed in the low voltage device region, so that the gate oxide film thinner than the gate oxide film formed in the high voltage device region is formed.
As in the above, as the thin gate oxide film is formed in the low voltage device region, the leakage current through the gate insulating film is significantly increased. Due to this, there are problems that the power consumption of the device is increased and reliability of the device is lowered. Accordingly, there is a physical limit in reducing the thickness of the gate oxide film.
Furthermore, in case of the transistor of a p type electrode, a dopant implanted into the gate is infiltrated into the gate insulating film or what is more into the channel region of the semiconductor substrate to change the threshold voltage of the transistor, in the course of implementing an annealing process in order to improve the film quality of the gate electrode and form a LDD (lightly doped drain) region and a source/drain region.
In case of a n type transistor, hot carriers that obtained energy higher than the energy barrier at the interface of the semiconductor substrate and the gate insulating film by the electric field are introduced into the gate insulating film while moving from the source to the drain. Due to this, there are problems that the electric characteristic of the transistor is varied and reliability of the device is degraded.